The invention relates to a method for the address-decoded operation of a semiconductor memory device in accordance with claim 1 and to a semiconductor memory device in accordance with claim 4.
Semiconductor memory devices, for example DRAM memories, typically comprise at least one memory cell array in which a multiplicity of memory cells are arranged in a matrix-like manner. An individual memory cell is designed for storing binary data, i.e. a logic xe2x80x9c0xe2x80x9d or a logic xe2x80x9c1xe2x80x9d. These memory cells can be addressed in the matrix-like memory cell array by the specification of their assigned electrical address. The electrical address comprises, in a simplified fashion, a row specification and a column specification, i.e. an X value and a Y value.
However, modern semiconductor memory devices have complex memory cell arrays in which the so-called electrical address counting differs from the physical address counting. A physical address is in this case understood to be a physical position of a respective memory cell in the matrix-like memory cell array, which position is specified by X and Y coordinates. Consequently, if the intention is to address a specific memory cell with a physical address (X; Y), then the electrical address (Xxe2x80x2; Yxe2x80x2) assigned to this memory cell must be known. Only if the physical addressing coincides with the electrical addressing can a memory cell with the physical position (X=5; Y=1), for example, be addressed by the inputting of the electrical address (Xxe2x80x2=5; Yxe2x80x2=1). Generally, however, in order to address the memory cell with the specified physical address, it is necessary to input an electrical address that deviates therefrom, e.g. (Xxe2x80x2=7; Yxe2x80x2=9).
This divergence of physical and electrical address counting causes considerable problems during the testing of the memory cell array which follows the fabrication of the semiconductor device. Thus, during the testing of the memory cell array, particular attention has to be directed toward a possibly functionally harmful interaction of adjacent memory cells. By way of example, the physical memory state of one memory cell (e.g. a positively or negatively charged storage capacitor) can influence an adjacent memory cell such that a write or read operation of this memory cell would lead to an incorrect result. In order to be able to preclude such possibly functionally harmful proximity effects of memory cells in the memory cell array, the cell array must be able to be brought into predetermined data topologies during the testing of the semiconductor device. A test of the memory cell array may, for example, involve testing whether error-free operation of the memory cell array is possible even when a chessboard topology of memory cells in a first and a second physical memory state (for example negatively and positively charged storage capacitors) is generated in the memory cell array.
In the same way, the order of access to the memory cells must also be taken into consideration during the testing of the memory cell array. In addition to the description of the test sequence of the semiconductor memory device, the so-called pattern encompassing the type of access, order of access and data topology, it is necessary, however, in modern semiconductor memory devices in which the physical and electrical address counting diverge, to program a so-called address scrambling in the test system used. This is because if the intention is to generate, for example, a chessboard topology in the memory cell array, then the test system must know the mapping or assignment of the electrical to the physical addresses of the memory cells. In order to bring a specific memory cell with a physical address (X; Y) into a specific physical memory state, the external test system must possess the assignment information in order to be able to output the electrical address required for addressing this memory cell to the semiconductor memory device.
On account of the continual advancing optimization of chip area and performance of modern semi-conductor memory devices, every new semiconductor memory device typically has a new, dedicated memory architecture, as a result of which there is a change in the items of assignment information between physical and electrical address counting. Consequently, every new semiconductor memory device requires a different address scrambling which must be programmed individually for this semiconductor memory device in the external test system. The programming of the external test systems is thus dependent on the respective semiconductor memory devices to be tested (the so-called DUT (device under test)). In many, in particular older, test systems, on account of the required data topologies whose complexity is constantly increasing, the program flexibility thereof no longer suffices for the required address scrambling. In any event, the programming of the test systems is very complicated and prone to errors.
Since external test systems are not subject to a uniform standard, moreover, each test system must be programmed individually. However, a semiconductor memory device typically passes through various test areas (for example bench, front-end test, back-end test and burn-in), various external test systems being used in each test area. An added difficulty is that a plurality of different test systems are possibly used within these test areas. By way of example, HP, Mosaid, IMS are used for the bench tests, Advantest and Teradyne are used for the front-end test and back-end test, and MTX and ANDO are used for the burn-in test. Individual address scrambling methods have to be programmed, if appropriate, for all these different test systems.
In view of the disadvantages mentioned above, it is an object of the invention to specify a semiconductor memory device which can be tested in a simple manner by different external test systems. Furthermore, it is an object of the invention to specify a corresponding method.
According to the invention, a method for the address-decoded operation of a semiconductor memory device, in particular of a semiconductor memory device according to the invention, comprises the following steps:
provision of the semiconductor memory device having at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions, each of the memory cells being assigned a physical address (X; Y) corresponding to the physical position of the memory cell in the memory cell array and an electrical address (Xxe2x80x2; Yxe2x80x2) corresponding to the electrical addressing of the memory cell in the memory cell array;
inputting of a physical address (X; Y) of a memory cell of the memory cell array that is to be addressed into an address input device of the semiconductor memory device;
decoding of the input physical address (X; Y) into the assigned electrical address (Xxe2x80x2; Yxe2x80x2) of the memory cell to be addressed by an address decoder device of the semiconductor memory device; and
outputting of the electrical address (Xxe2x80x2; Yxe2x80x2) to the memory cell array in order to address the memory cell to be addressed.
The method for address-decoded operation according to the invention accordingly relates to a semiconductor memory device having a memory cell array which is matrix-like at least in regions. Each memory cell of the memory cell array thus has a physical address corresponding to its physical position in the memory cell array. By way of example, the very top left memory cell has the physical address (X=0; Y=0). Each memory cell is also assigned an electrical address whichxe2x80x94expressed in a simplified fashionxe2x80x94must be applied to the row and column decoders of the memory cell array in order to be able to effectively address said memory cell. If the physical and electrical address counting diverge in the semiconductor device, then the electrical address (Xxe2x80x2; Yxe2x80x2) deviates, if appropriate, from the physical address (X; Y) of the memory cell to be addressed.
In order to address a specific memory cell with the physical address (X; Y), the method according to the invention, in address-decoded operation, allows a simple addressing of this memory cell, however. Thus, the physical address of the memory cell to be addressed can be input directlyxe2x80x94for example from an external test systemxe2x80x94into an address input device of the semiconductor memory device. The semiconductor memory device comprises an address decoder device which decodes this input physical address into the assigned electrical address of the memory cell to be addressed. The xe2x80x9caddress scramblingxe2x80x9d is thus effected directly by the address decoder device on the semiconductor memory device. The electrical address thus decoded is subsequently output to the memory cell array (i.e. in particular to the row and column decoders) in order to address the memory cell to be addressed.
Consequently, the external test system advantageously need not contain any items of assignment or mapping information between physical and electrical address counting. Rather, it suffices for the external test system to address the memory cell to be addressed directly with its physical address (X; Y), since the address decoder device ensures that the electrical address assigned to this physical address is output for the proper addressing of the memory cell to be addressed. This considerably simplifies the programming of external test systems, since the complicated programming, prone to errors, of the address scrambling can be completely omitted. Advantageously, the semiconductor memory device can also be operated in an address normal mode, in which the address decoder device performs no such decoding of input addresses. Instead of this, in such a modexe2x80x94in a customary mannerxe2x80x94input addresses can be output directly as electrical addresses to the memory cell array.
The invention furthermore proposes a method for the data-decoded operation of a semiconductor memory device which can preferably be combined with the method for address-decoded operation according to the invention and comprises the following steps:
provision of the semiconductor memory device having at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions,
inputting of data that are to be written to the memory cell to be addressed and have two logic data states into a data input device of the semiconductor memory device;
decoding of the input data by a data decoder device of the semiconductor device in such a way that
in the event of data inputting of the first logic data state, such a decoded data state is generated which is assigned to a predetermined first physical memory state of the memory cell to be addressed, and
in the event of data inputting of the second logic data state, such a decoded data state is generated which is assigned to a predetermined second physical memory state of the memory cell to be addressed; and
outputting of the decoded data state to the memory cell array in order to bring the memory cell to be addressed into the respective physical memory state.
In addition to an xe2x80x9caddress scramblingxe2x80x9d which is implemented internally in the semiconductor memory device or externally in a test system, a so-called xe2x80x9cdata scramblingxe2x80x9d is often necessary, too, in modern memory architectures. Thus, in specific memory architectures, by way of example, a logic xe2x80x9c0xe2x80x9d is stored, depending on the memory cell, in the form of a first physical state (for example a negatively charged storage capacitor) or a second physical state (for example a positively charged storage capacitor). In particular, the memory cell array may contain xe2x80x9cnormalxe2x80x9d memory cells, in which a logic xe2x80x9c0xe2x80x9d are stored by the first physical memory state, and xe2x80x9cinvertedxe2x80x9d memory cells, in which a logic xe2x80x9c0xe2x80x9d, are stored by the second physical state. In order to be able to determine whether a memory cell to be addressed is a xe2x80x9cnormalxe2x80x9d or an xe2x80x9cinvertedxe2x80x9d memory cell, the electrical and/or physical address of said memory cell must be known.
Consequently, in order to be able to generate a predetermined data topology in the cell array of a semiconductor memory device with an architecture of this type, a data scrambling must be carried out. This was conventionally done by programming the information required for the xe2x80x9cdata scramblingxe2x80x9d in the external test system. In order, according to a conventional method, for example, to generate a uniform-solid data topology of memory cells with positively charged storage capacitors, the external test system in each case output a logic xe2x80x9c0xe2x80x9d to the xe2x80x9cnormalxe2x80x9d memory cells and in each case a logic xe2x80x9c1xe2x80x9d to the xe2x80x9cinvertedxe2x80x9d memory cells. This xe2x80x9cdata scramblingxe2x80x9d resulted in complicated programming, prone to errors, of the external test systems.
In accordance with the preferred method according to the invention, the xe2x80x9cdata scramblingxe2x80x9d is effected by a data decoder device which is a component part of the semiconductor device. Consequently, the items of xe2x80x9cdata scramblingxe2x80x9d information need no longer be part of the external test system. Instead, for all the memory cellsxe2x80x94irrespective of whether xe2x80x9cnormalxe2x80x9d or xe2x80x9cinvertedxe2x80x9d memory cells are involvedxe2x80x94a first logic data state can be input by the external test system, for example, into the data input device of the semiconductor device if the predetermined first physical memory state is intended to be generated in the memory cell to be addressed. Conversely, the second logic data state can be input into the data input device of the semiconductor memory device if the memory cell to be addressed is intended to be brought into the predetermined second physical memory state.
In accordance with a further preferred embodiment, the method according to the invention is additionally designed for the topology-generating operation of the semiconductor memory device and comprises the following further steps:
inputting of data that are to be written to the memory cell to be addressed and have two logic data states to a data input device of the semiconductor memory device;
outputting of such data to the memory cell array that a predetermined and/or programmable data topology, in particular a chessboard, line, multiple-line and/or a uniform-solid topology of memory cells in a first and a second physical memory state, is generated, preferably independently of the data input into the data input device, at least in a part of the memory cell array.
A xe2x80x9csemiautomaticxe2x80x9d topology-generating method is thus provided, whereby frequently recurring, typical data topologies can be implemented in a simple manner in the memory cell array. By way of example, for test purposes, the memory cell array of a semiconductor memory device is often put into a so-called chessboard topology in which the memory cells are in a chessboardxe2x80x94like pattern in the first or the second physical memory state (for example a negatively or positively charged storage capacitor).
In topology-generating operation, by way of example, the external test system need not output data corresponding to a chessboard pattern to the semiconductor memory device. Instead, it suffices, for example, if arbitrary data are input into the data input device of the semiconductor memory device, since, in topology-generating operation, such data are automatically output to the memory cell array that the predetermined and/or programmable data topology is generated (semiautomatically) at least in a part of the cell array. The data which are to be output to the memory cell array and correspond to the data topology to be generated are preferably provided by the data decoder device.
Preferably, in topology-generating operation, various generation methods are fixedly preprogrammed into the data decoder device and can be selected, in particular corresponding methods for generating a chessboard, line, multiple-line and/or uniform-solid topologies. In this case, it may be provided that the predetermined or predeterminable and/or programmable topologies are selected by means of control signals to be input, if appropriate in conjunction with a data signal that is likewise to be input. By way of example, the basic topology (e.g. a chessboard topology) can be selected by means of the control signal and a special topology of said basic topology (e.g. a chessboard topology with a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the top left corner) can be selected by means of the data signal to be input, so that a selection between complementary topologies is possible by means of the data to be input However, the topologies can also be selected completely independently of the data input into the data input device, exclusively using the control signal.
The possibility of being able to program the data topology, which is intended to be created during topology-generating operation, externally into the semiconductor memory device is particularly preferred. By way of example, at the beginning of topology-generating operation, firstly the geometry of the data topology to be generated is communicated from the external test system to the semiconductor memory device, and is subsequently generated.
According to the invention, a semiconductor memory device comprises
at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions, each of the memory cells being assigned a physical address corresponding to the physical position of the memory cell in the memory cell array and an electrical address corresponding to the electrical addressing of the memory cell in the memory cell array;
at least one address input device for address inputting of the physical or the electrical address of a memory cell of the memory cell array that is to be addressed; and
at least one address decoder device which is signal-connected to the address input device and the memory cell array,
the address decoder device, in an address decoder mode, being designed, in the event of address inputting of the physical address of the memory cell to be addressed, to output the electrical address assigned thereto to the memory cell array in order to address the memory cell to be addressed.
According to the invention, the address decoder device of the semiconductor memory device has an address decoder mode in which an xe2x80x9caddress scramblingxe2x80x9d of addresses which are input into the address input device is performed. Consequently, by way of example, an external test system can directly address a memory cell of the memory cell array that is to be addressed by inputting the physical address of the memory cell to be addressed into the address input device. The address decoder device decodes this input physical address into the electrical address assigned to the memory cell to be addressed and outputs this assigned electrical address to the memory cell array (for example the row and column decoders), in order to address the memory cell to be addressed. The fact that the external test system can address the memory cells in a simple manner by outputting the physical addresses advantageously obviates the complicated programming of the xe2x80x9caddress scramblingxe2x80x9d in the external test system.
The address input device of the semiconductor memory device is equally also designed for the address inputting of electrical addresses of memory cells to be addressed. Such address inputting of the electrical addresses is effected in particular when the address decoder device is not in the address decoder mode.
In accordance with a preferred embodiment, the address decoder device has at least the address decoder mode and an address normal mode, which can preferably be selected externally, an the address decoder mode, in the event of address inputting of the physical address of the memory cell to be addressed, the assigned electrical address being output to the memory cell array and in the address normal mode, the input address being output to the memory cell array.
Whereas an xe2x80x9caddress scramblingxe2x80x9d of the input physical addresses into the assigned electrical addresses is effected in the address decoder mode of the address decoder device, the semiconductor memory device behaves like a conventional semiconductor memory device in the address normal mode of the address decoder device. In the address normal mode, the input addressesxe2x80x94which are electrical addresses of memory cells of the memory cell arrayxe2x80x94are output directly for addressing purposes to the memory cell array without an additional decoding of these input addresses having been effected. For example, for this purpose, the addresses which are input into the address input device in the address normal mode are looped through directly to the memory cell array, bypassing the address decoder device, and the input addresses may, if appropriate, be subjected to other signal-processing processes.
The address decoder mode and the address normal mode of the address decoder device can preferably be selected externally, for example by means of a control signal that is to be input into the semiconductor memory device In order that the user of the semiconductor memory device does not inadvertently enter into the address decoder mode, it is recommended that the control signal which serves for the activation of the address decoder mode be suitably encrypted. It is possible, after the conclusion of all the test methods of the semiconductor memory device, to bring the address decoder device permanently into the address normal mode by the destruction of selection fuses of the semiconductor memory device that are provided for this purpose, for example.
In accordance with a further aspect of the invention, the semiconductor memory device, which may preferably be embodied as described above, comprises
at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions,
at least one data input device for data that are to be written to the memory cell to be addressed and have two logic data states,
at least one data decoder device which is signal-connected to the data input device, an address input device and the memory cell array, the address input device preferably being connected to the data decoder device via an address decoder device, the data decoder device, in a data decoder mode, being designed,
in the event of data inputting of the first logic data state, to output such a decoded data state to the memory cell array that the memory cell to be addressed is brought into a predetermined first physical memory state, and, in the event of data inputting of the second logic data state, to output such a decoded data state to the memory cell array that the memory cell to be addressed is brought into a predetermined second physical memory state.
The data decoder device thus enables, in its data decoder mode, a xe2x80x9cdata scramblingxe2x80x9d of logic data that are to be input into the data input device. Since the data decoder device is integrated into the semiconductor memory device, a complicated xe2x80x9cdata scramblingxe2x80x9d method, prone to errors, need not be programmed in an external test system, for example. Instead, the external test system can, in a simple manner, output a first logic data state to the semiconductor device if the memory cell to be addressed is intended to be brought into a first physical memory state. Accordinglyxe2x80x94irrespective of whether the memory cell to be addressed is a xe2x80x9cnormalxe2x80x9d or xe2x80x9cinvertedxe2x80x9d memory cellxe2x80x94a second logic data state can be output to the semiconductor memory device in order to transfer the memory cell to be addressed into the second physical memory state. In order to be able to decide whether the memory cell to be addressed is a xe2x80x9cnormalxe2x80x9d or an xe2x80x9cinvertedxe2x80x9d memory cell, the data decoder device requires the address information of the memory cell to be addressed. The data decoder device obtains this address information preferably from the address decoder device orxe2x80x94if the address scrambling is not integrated in the semiconductor memory devicexe2x80x94directly from an address decoder device of the external test system.
In accordance with a further preferred embodiment, the semiconductor memory device comprises at least one data output device for data that are to be read from the memory cell to be addressed and have two logic data states, the data decoder device being signal-connected to the data output device and being designed to output data with the first logic data state to the data output device if the memory cell to be addressed is in the first physical memory state and to output data with the second logic data state to the data output device if the memory cell is in the second physical memory state.
Consequently, in the data decoder mode, data read from the memory cell array are xe2x80x9cdescrambledxe2x80x9d before they are output to the data output device of the semiconductor memory device. Irrespective of whether the memory cell that is to be addressed and is intended to be read is a xe2x80x9cnormalxe2x80x9d or an xe2x80x9cinvertedxe2x80x9d cell, logic data states which correspond directly to the physical memory states of the memory cell to be addressed are thus output to the data output device. If an external test system receives, for example, a first logic data state from the data output device of the semiconductor memory device, then it can directly conclude that the memory cell to be read must have been in the first physical memory state. Consequently, a conventionally required inverted xe2x80x9cdata scramblingxe2x80x9d does not have to be programmed in the external test system.
The data decoder device is preferably signal-connected to an address register of the address decoder device. In order to be able to carry out the xe2x80x9cdata scramblingxe2x80x9d, the data decoder device requiresxe2x80x94as already explained abovexe2x80x94the address information items of the memory cell to be addressed, in order to be able to assess whether a xe2x80x9cnormalxe2x80x9d or an xe2x80x9cinvertedxe2x80x9d memory cell is involved. These address information items are made available to the data decoder device by the address decoder device by means of the address register.
In accordance with a further preferred embodiment, the data decoder device has at least the data decoder mode and a data normal mode, which can preferably be selected externally, decoding of data being effected only in the data decoder mode.
Consequently, the xe2x80x9cdata scramblingxe2x80x9d by the data decoder device is effected only when the data decoder mode of the data decoder device has been selected, for example, by a control signal that is to be input externally. Such activation of the data decoder mode can be effected, for example, in a similar manner to the activation of the address decoder mode of the address decoder device. If the data decoder device is in the data normal mode, it behaves similarly to a conventional semiconductor memory device, i.e. the input and output data are not subjected to an additional xe2x80x9cdata scramblingxe2x80x9d method by the data decoder device.
In accordance with a further preferred embodiment, the data decoder device has a preferably externally selectable topology-generating mode which is designed in such a way that, preferably independently of the data input into the data input device, such data are output to the memory cell array that a predetermined and/or programmable data topology, in particular a chessboard, line, multiple-line and/or a uniform-solid topology of memory cells in the first and the second physical memory state, is generated at least in a part of the memory cell array.
Consequently, in the topology-generating mode, the memory cell array can be brought in a simple manner into a predetermined or predeterminable and/or programmable topology of physical memory states of the memory cells. Preferably, the data which are input into the data input device of the semiconductor memory device by the external test system need not be designed for the generation of the desired data topology. Rather, preferably arbitrary data can be input into the data input device of the semiconductor memory device by the test system, since, in the topology-generating mode, the data decoder device outputs suitable data to the memory cell array in accordance with the desired data topology. In this case, it may be provided that the predetermined or predeterminable and/or programmable topologies are selected by means of control signals to be input, if appropriate in conjunction with a data signal that is likewise to be input. By way of example, the basic topology (e.g. a chessboard topology) can be selected by means of the control signal and a special topology of said basic topology (e.g. a chessboard topology with a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the top left corner) can be selected by means of the data signal to be input, so that a selection between complementary topologies is possible by means of the data to be input. However, the topologies can also be selected completely independently of the data input into the data input device, exclusively using the control signal.
The invention is described below by way of example with reference to accompanying drawings of a synchronous semiconductor memory device. In the figures: